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INTEGRATED CIRCUITS
PCA9501 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
Product data Supersedes data of 2002 Sep 27 2003 Sep 12
Philips Semiconductors
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
DESCRIPTION
The PCA9501 is an 8-bit I/O expander with an on-board 2-kbit EEPROM. The I/O expandable eight quasi bidirectional data pins can be independently assigned as inputs or outputs to monitor board level status or activate indicator devices such as LEDs. The system master writes to the I/O configuration bits in the same way as for the PCF8574. The data for each Input or Output is kept in the corresponding Input or Output register. The system master can read all registers.
FEATURES
* 8 general purpose input/output expander/collector * Replacement for PCF8574 with integrated 2-kbit EEPROM * Internal 256 x 8 EEPROM * Self timed write cycle (5 ms typ) * 16 byte page write operation * I2C and SMBus interface logic * Internal power-on reset * Noise filter on SCL/SDA inputs * Active low interrupt output * 6 address pins allowing up to 64 devices on the I2C/SMBus * No glitch on power-up * Supports hot insertion * Power-up with all channels configured as inputs * Low standby current * Operating power supply voltage range of 2.5 V to 3.6 V * 5 V tolerant inputs/outputs * 0 to 400 kHz clock frequency * ESD protection exceeds 2000 V HBM per JESD22-A114, * Latch-up testing is done to JESDEC Standard JESD78 which * Packages offered: SO20, TSSOP20, HVQFN20
ORDERING INFORMATION
PACKAGES 20-pin plastic SO 20-Pin Plastic TSSOP 20-Pin Plastic HVQFN TEMPERATURE RANGE -40 to +85 C -40 to +85 C -40 to +85 C exceeds 100 mA 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
The EEPROM can be used to store error codes or board manufacturing data for read-back by application software for diagnostic purposes and are included in the I/O expander package. The PCA9501 Active-LOW open-drain interrupt output is activated when any input state differes from its corresponding input port register state. It is used to indicate to the system master that an input state has changed and the device needs to be interrogated. The PCA9501 has six address pins with internal pull-up resistors allowing up to 64 devices to share the common two wire I2C software protocol serial data bus. The fixed GPIO address starts with "1" and the fixed EEPROM I2C address starts with "0", so the PCA9501 appears as two separate devices to the bus master. The PCA9501 supports hot insertion to facilitate usage in removable cards on backplane systems.
ORDER CODE PCA9501D PCA9501PW PCA9501BS
TOPSIDE MARK PCA9501D PCA9501 9501
DRAWING NUMBER SOT163-1 SOT360-1 SOT662-1
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging. SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent. I2C is a trademark of Philips Semiconductors Corporation.
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
PIN CONFIGURATION - SO, TSSOP
A0 1 A1 2 A2 3 I/O0 4 I/O1 5 I/O2 6 I/O3 7 INT 8 A5 9 VSS 10 PCA9501 20 VDD 19 SDA 18 SCL 17 WC 16 I/O7 15 I/O6 14 I/O5 13 I/O4 12 A3 11 A4 SW00903
PIN CONFIGURATION - HVQFN
A1 20 A0 VDD SDA SCL 19 18 17 16 15 WC 14 I/O7 13 I/O6 12 I/O5 11 I/O4 10 A3 6 7 8 VSS 9 A4
A2 I/O0 I/O1 I/O2 I/O3
1 2 3 4 5
INT A5
TOP VIEW
SW02017
Figure 1. Pin configuration - SO, TSSOP Figure 2. Pin configuration - HVQFN
PIN DESCRIPTION
PIN NUMBER SO, TSSOP 1, 2, 3, 9, 11, 12 4, 5, 6, 7 8 10 13, 14, 15, 16 17 18 19 20 HVQFN 19, 20, 1, 7, 9, 10 2, 3, 4, 5 6 8 11, 12, 13, 14 15 16 17 18 A0-5 I/O0-3 INT VSS I/O4-7 WC SCL SDA VDD Address lines (internal pull-up) Quasi-bidirectional I/O pins Active low interrupt output (open drain) Supply ground Quasi-bidirectional I/O pins Active low write control pin I2C serial clock I2C serial data Supply voltage SYMBOL NAME AND FUNCTION
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
BLOCK DIAGRAM
PCA9501
300 k
A0 A1 A2 A3 A4 A5 SCL SDA INPUT FILTER I2C/SMBus CONTROL 8-BIT INPUT/ OUTPUT PORTS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 VCC VDD VSS POWER-ON RESET LP FILTER INT
WRITE pulse READ pulse
WC
EEPROM 256 x 8
SW01077
Figure 3. Block diagram
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
FUNCTIONAL DESCRIPTION
VDD WRITE PULSE 100 A DATA FROM SHIFT REGISTER D FF CI S POWER-ON RESET VSS I/O0 TO I/O7 Q
D FF READ PULSE CI S
Q
DATA TO SHIFT REGISTER
TO INTERRUPT LOGIC SW00788
Figure 4. Simplified schematic diagram of each I/O
DEVICE ADDRESSING
Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9501 is shown in Figure 5. Internal pullup resistors are incorporated on the hardware selectable address pins.
SLAVE ADDRESS
SLAVE ADDRESS
0
A5
A4
A3
A2
A1
A0
R/W
1
A5
A4
A3
A2
A1
A0
R/W
FIXED (a) I/O EXPANDER (b) MEMORY
HARDWARE PROGRAMMABLE a.
FIXED
HARDWARE PROGRAMMABLE b.
SW02006
Figure 5. PCA9501 slave addresses The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write operation.
CONTROL REGISTER
The PCA9501 contains a single 8-bit register called the Control Register, which can be written and read via the I2C bus. This register is sent after a successful acknowledgment of the slave address. It contains the I/O operation information.
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
I/O OPERATIONS (see also Figure 4)
Each of the PCA9501's eight I/Os can be independently used as an input or output. Output data is transmitted to the port by the I/O WRITE mode (see Figure 6). Input I/O data is transferred from the port to the microcontroller by the READ mode (See Figure 7).
SCL
1
2
3
4
5
6
7
8
SLAVE ADDRESS (I/O EXPANDER)
DATA TO PORT
DATA TO PORT
SDA
S
0
A5
A4
A3 A2
A1
A0
0
A
DATA 1
A
DATA 2
A
START CONDITION WRITE TO PORT
R/W
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
DATA OUT FROM PORT t pv
DATA 1 VALID t pv
DATA 2 VALID
SW00649
Figure 6. I/O WRITE mode (output)
SLAVE ADDRESS (I/O EXPANDER)
DATA FROM PORT
DATA FROM PORT
SDA
S
0
A5
A4
A3 A2
A1
A0
1
A
DATA 1
A
DATA 4
1
P
START CONDITION READ FROM PORT
R/W
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM MASTER
STOP CONDITION
DATA INTO PORT
DATA 1 t ph
DATA 2
DATA 3 t ps
DATA 4
INT t iv t ir SW00650
Figure 7. I/O READ mode (input)
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
Quasi-bidirectional I/Os (see Figure 8)
A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs.
SLAVE ADDRESS (I/O EXPANDER)
DATA TO PORT
DATA TO PORT
SDA
S
0
A5
A4
A3
A2
A1
A0
0
A
1
A
0
A
P
START CONDITION
R/W
ACKNOWLEDGE FROM SLAVE
I/O3
ACKNOWLEDGE FROM SLAVE
I/O3
SCL
1
2
3
4
5
6
7
8
I/O3 OUTPUT VOLTAGE
I/O3 PULL-UP OUTPUT CURRENT
IOHt
IOH
SW00904
Figure 8. Transient pull-up current IOHt while I/O3 changes from LOW-to-HIGH and back to LOW
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
Interrupt (see Figs 9 and 12)
The PCA9501 provides an open drain output (INT) which can be fed to a corresponding input of the microcontroller. This gives these chips a type of master function which can initiate an action elsewhere in the system. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv the signal INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from or written to the port which has generated the interrupt.
Resetting occurs as follows: the SCL signal
* In the READ mode at the acknowledge bit after the rising edge of * In the WRITE mode at the acknowledge bit after the
HIGH-to-LOW transition of the SCL signal
* Returning of the port data to its original setting. * Interrupts which occur during the acknowledge clock pulse may
be lost (or very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting will be detected and, after the next rising clock edge, will be transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit.
VDD
PCA9501 (1)
PCA9501 (2)
PCA9501 (16)
INT MICROCONTROLLER INT
INT
INT
SW00790
Figure 9. Application of multiple PCA9501s with interrupt
SLAVE ADDRESS (I/O EXPANDER)
DATA FROM PORT
SDA
S
0
A5
A4
A3
A2
A1
A0
1
A
1
1
P
START CONDITION SCL 1 2 3 4 5 6 7
R/W 8
ACKNOWLEDGE FROM SLAVE
I/O5
STOP CONDITION
DATA INTO I/O5
INT t iv t ir SW00791
Figure 10. Interrupt generated by a change of input to I/O5
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
MEMORY OPERATIONS Write operations
Write operations require an additional address field to indicate the memory address location to be written. The address field is eight bits long providing access to any one of the 256 words of memory. There are two types of write operations, byte write and page write. Write operation is possible when WC control pin put at a low logic level (0). When this control signal is set at 1, write operation is not possible and data in the memory is protected. Byte Write and Page Write explained below assume that Write Control pin (WC) is set to 0. Byte Write (see Figure 11) To perform a byte write the start condition is followed by the memory slave address and the R/W bit set to 0. The PCA9501 will respond with an acknowledge and then consider the next eight bits sent as
the word address and the eight bits after the word address as the data. The PCA9501 will issue an acknowledge after the receipt of both the word address and the data. To terminate the data transfer the master issues the stop condition, initiating the internal write cycle to the non-volatile memory. Only write and read operations to the quasi-bidirectional I/Os are allowed during the internal write cycle. Page Write (see Figure 12) A page write is initiated in the same way as the byte write, if after sending the first word of data, the stop condition is not received the PCA9501 considers subsequent words as data. After each data word the PCA9501 responds with an acknowledge and the four least significant bits of the memory address field are incremented. Should the master not send a stop condition after 16 data words the address counter will return to its initial value and overwrite the data previously written. After the receipt of the stop condition the inputs will behave as with the byte write during the internal write cycle.
SLAVE ADDRESS (MEMORY)
WORD ADDRESS
DATA
SDA
S
1
A5 A4 A3 A2 A1 A0 0
A
A
A
P
START CONDITION
R/W ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
STOP CONDITION. WRITE TO THE MEMORY IS PERFORMED SW00651
Figure 11. Byte write
SLAVE ADDRESS (MEMORY)
WORD ADDRESS
DATA TO MEMORY
DATA TO MEMORY
SDA
S
1
A5 A4 A3 A2 A1 A0 0
A
A
DATA n
A
DATA n + 3
A
P
START CONDITION
R/W ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
STOP CONDITION. WRITE TO THE MEMORY IS PERFORMED
SW00652
Figure 12. Page Write
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Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
Read operations
PCA9501 read operations are initiated in an identical manner to write operations with the exception that the memory slave address' R/W bit is set to a one. There are three types of read operations; current address, random and sequential. Current Address Read (see Figure 13) The PCA9501 contains an internal address counter that increments after each read or write access, as a result if the last word accessed was at address n then the address counter contains the address n+1. When the PCA9501 receives its memory slave address with the R/W bit set to one it issues an acknowledge and uses the next eight clocks to transmit the data contained at the address stored in the address counter. The master ceases the transmission by issuing the stop condition after the eighth bit. There is no ninth clock cycle for the acknowledge. Random Read (see Figure 14) The PCA9501's random read mode allows the address to be read from to be specified by the master. This is done by performing a dummy write to set the address counter to the location to be read.
The master must perform a byte write to the address location to be read, but instead of transmitting the data after receiving the acknowledge from the PCA9501 the master reissues the start condition and memory slave address with the R/W bit set to one. The PCA9501 will then transmit an acknowledge and use the next eight clock cycles to transmit the data contained in the addressed location. The master ceases the transmission by issuing the stop condition after the eighth bit, omitting the ninth clock cycle acknowledge. Sequential Read (see Figure 15) The PCA9501 sequential read is an extension of either the current address read or random read. If the master doesn't issue a stop condition after it has received the eighth data bit, but instead issues an acknowledge, the PCA9501 will increment the address counter and use the next eight cycles to transmit the data from that location. The master can continue this process to read the contents of the entire memory. Upon reaching address 255 the counter will return to address 0 and continue transmitting data until a stop condition is received. The master ceases the transmission by issuing the stop condition after the eighth bit, omitting the ninth clock cycle acknowledge.
SLAVE ADDRESS (MEMORY)
DATA FROM MEMORY
SDA
S
1
A5
A4
A3
A2
A1 A0
1
A
P
START CONDITION
R/W
ACKNOWLEDGE FROM SLAVE
STOP CONDITION
SW00653
Figure 13. Current Address Read
SLAVE ADDRESS (MEMORY)
WORD ADDRESS
SLAVE ADDRESS (MEMORY)
DATA FROM MEMORY
SDA
S
1
A5 A4 A3 A2 A1 A0 0 R/W
A
A ACKNOWLEDGE FROM SLAVE
S
1 A5 A4 A3 A2 A1 A0 R/W
1
A
P
START CONDITION
ACKNOWLEDGE FROM SLAVE
START CONDITION
ACKNOWLEDGE FROM SLAVE
STOP CONDITION
SW00654
Figure 14. Random Read
SLAVE ADDRESS (MEMORY)
DATA FROM MEMORY
DATA FROM MEMORY
DATA FROM MEMORY
SDA
S
1
A5 A4 A3 A2 A1 A0 R/W
1
A
DATA n
A
DATA n+1
A
DATA n+X
P
START CONDITION
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MASTER SW00655
STOP CONDITION
Figure 15. Sequential Read
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Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 17).
Bit transfer
One data bit is transferred during each clock phase. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (See Figure 16).
System configuration
A device generating a message is a "transmitter", a device receiving is the "receiver". The device that controls the message is the "master" and the devices which are controlled by the master are the "slaves" (see Figure 18).
SDA
SCL
DATA LINE STABLE; DATA VALID
CHANGE OF DATA ALLOWED
SW00542
Figure 16. Bit transfer
SDA
SDA
SCL S START CONDITION P STOP CONDITION
SCL
SW00543
Figure 17. Definition of start and stop conditions
SDA SCL
MASTER TRANSMITTER/ RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
SW00544
Figure 18. System configuration
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Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
Acknowledge (see Figure 19)
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked
out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT BY TRANSMITTER NOT ACKNOWLEDGE
DATA OUTPUT BY RECEIVER ACKNOWLEDGE
SCL FROM MASTER S START CONDITION
1
2
8
9
CLOCK PULSE FOR ACKNOWLEDGEMENT
SW00545
Figure 19. Acknowledgment on the I2C-bus
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Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
TYPICAL APPLICATION Applications
* Board version tracking and configuration * Board health monitoring and status reporting * Multi-card systems in Telecom, Networking, and Base Station
Infrastructure Equipment
* Field recall and troubleshooting functions for installed boards
UP TO 64 CARDS
* General-purpose integrated I/O with memory * Replacement for PCF8574 with integrated 2-kbit EEPROM * Bus master sees GPIO and EEPROM as two separate devices * Six hardware address pins allow up to 64 PCA9501s to be located
in the same I2C/SMBus
I2C
ASIC
I2C
CPU OR C BACKPLANE
I2C
I2C
CONFIGURATION CONTROL
I2C
PCA9501
CONTROL INPUTS GPIO MONITORING AND CONTROL ALARM LEDs EEPROM
I2C
CARD ID, SUBROUTINES, CONFIGURATION DATA, OR REVISION HISTORY
SW02007
Figure 20. Typical application A central processor/controller typically located on the system main board can use the 400 kHz I2C/SMBus to poll the PCA9501 devices located on the system cards for status or version control type of information. The PCA9501 may be programmed at manufacturing to store information regarding board build, firmware version, manufacturer identification, configuration option data... Alternately, these devices can be used as convenient interface for board configuration, thereby utilizing the I2C/SMBus as an intra-system communication bus.
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Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
TYPICAL APPLICATION
VDD 2 k VDD SCL SDA MASTER CONTROLLER INT 1.6 k 1.6 k 1.1 k 2 k (optional) VDD SCL SDA I/01 INT I/02 GND I/03 PCA9501 I/04 SUBSYSTEM 2 (e.g. counter) RESET INT I/00 SUBSYSTEM 1 (e.g. temp sensor)
A5 A4
I/05
A Controlled Switch (e.g. CBT device) ENABLE
I/06
A3 A2 A1 A0 VSS I/07
B
ALARM SUBSYSTEM 3 (e.g. alarm system)
NOTE: GPIO device address configured as 0110000 for this example EEPROM device address configured as 1110000 for this example I/00, I/02, I/03, configured as outputs I/01, I/04, I/05, configured as inputs I/006, I/07, are not used and have to be configured as outputs
VDD
SW01078
Figure 21. Typical application
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Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. SYMBOL VCC VI II IO IDD ISS Ptot PO TSTG TAMB Supply Voltage Input Voltage DC Input Current DC Output Current Supply Current Supply Current Total Power Dissipation Total Power Dissipation per Output Storage Temperature Operating Temperature PARAMETER MIN -0.5 VSS - 0.5 -20 -25 -100 -100 -- -- -65 -40 MAX 4.0 5.5 20 25 100 100 400 100 +150 +85 UNIT V V mA mA mA mA mW mW _C _C
DC ELECTRICAL CHARACTERISTICS
Tamb = -40 _C to +85 _C unless otherwise specified; VCC = 3.3 V SYMBOL Supply VDD IDDQ IDD1 IDD2 VPOR VIL VIH IOL IL CI VIL VIH IIHL(max) IOL IOH IOHt CI CO VIL VIH IL Supply Voltage Standby Current; A0 thru A5, WC = HIGH Supply Current Read Supply Current Write Power on Reset Voltage Input LOW voltage Input HIGH voltage Output LOW current @ VOL = 0.4 V Input leakage current @ VI = VDD or VSS Input capacitance @ VI = VSS Input LOW voltage Input HIGH voltage Input current through protection diodes Output LOW current @ VOL = 1 V Output HIGH current @ VOH = Vss Transient pull-up current Input Capacitance Output Capacitance Input LOW voltage Input HIGH voltage Input leakage current @ VI = VDD Input leakage (pull-up) current @ VI = VSS Interrupt output INT IOL IL Low level output current; VOL = 0.4 V Leakage current @ VI = VDD or VSS 1.6 -1 -- -- -- +1 mA A 2.5 -- -- -- -- -0.5 0.7 VDD 3 -1 -- -0.5 0.7 VDD -400 10 30 -- -- -- -0.5 0.7 VDD -1 10 3.3 -- -- -- -- -- -- -- -- -- -- -- -- 25 100 2 -- -- -- -- -- 25 3.6 60 1 2 2.4 0.3 VDD 5.5 -- 1 7 0.3 VDD 5.5 400 -- 300 -- 10 10 0.3 VDD 5.5 1 100 V A mA mA V V V mA A pF V V A mA A mA pF pF V V A A PARAMETER MIN TYP MAX UNIT
Input SCL; input, output SDA
I/O Expander Port
Address Inputs A0 thru A5, WC input
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
NON-VOLATILE STORAGE SPECIFICATIONS
PARAMETER Memory cell data retention Number of memory cell write cycles 10 years minimum 100,000 cycles minimum SPECIFICATION
I2C-BUS TIMING CHARACTERISTICS
SYMBOL I2C-bus timing (see Figure 22; Note 1) fSCL tSW tBUF tSU;STA tHD;STA tr tf tSU;DAT tHD;DAT tVD;DAT tSU;STO SCL clock frequency tolerable spike width on bus bus free time START condition set-up time START condition hold time SCL and SDA rise time SCL and SDA fall time data set-up time data hold time SCL LOW to data out valid STOP condition set-up time -- -- 1.3 0.6 0.6 -- -- 250 0 -- 0.6 -- -- -- -- -- -- -- -- -- -- -- 400 50 -- -- -- 0.3 0.3 -- -- 1.0 -- kHz ns s s s s s ns ns s s PARAMETER MIN. TYP. MAX. UNIT
NOTE: 1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD.
PORT TIMING CHARACTERISTICS
SYMBOL tpv tps tph tiv tir PARAMETER Output data valid; CL 100 pF Input data setup time; CL 100 pF Input data hold time; CL 100 pF Interrupt input data valid time; CL 100 pF Interrupt reset time; CL 100 pF MIN -- 0 4 -- -- TYP -- -- -- -- -- MAX 4 -- -- 4 4 UNIT s s s s s
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Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
handbook, full pagewidth PROTOCOL
START CONDITION (S)
BIT 7 MSB (A7)
BIT 6 (A6)
BIT 0 LSB (R/W)
ACKNOWLEDGE (A)
STOP CONDITION (P)
t
SU;STA
1 / f SCL
SCL
t
BUF
tr
t
f
SDA
t HD;STA
t
SU;DAT
t
HD;DAT
t
VD;DAT
MBD820
t SU;STO SW00561
Figure 22.
POWER-UP TIMING
SYMBOL tPUR
1
PARAMETER Power-up to Read Operation Power-up to Write Operation
MAX. 1 5
UNIT ms ms
tPUW1
NOTE: 1. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are guaranteed by design.
WRITE CYCLE LIMITS
SYMBOL tWR1 Write Cycle Time PARAMETER MIN. -- TYP. (5) 5 MAX. 10 UNIT ms
NOTE: 1. tWR is the maximum time that the device requires to perform the internal write operation.
Write Cycle Timing
SCL
SDA
8th Bit Word n
ACK tWR Stop Condition Start Condition SW00560 MEMORY ADDRESS
Figure 23.
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Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
SOLDERING Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our IC Package Databook (order code 9398 652 90011). seconds depending on heating method. Typical reflow temperatures range from 215 to 250C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45C. Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: followed by a smooth laminar wave) soldering technique should be used.
DIP
Soldering by dipping or by wave The maximum permissible temperature of the solder is 260C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400C, contact may be up to 5 seconds.
* A double-wave (a turbulent wave with high upward pressure * The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150C within 6 seconds. Typical dwell time is 4 seconds at 250C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonally opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320C.
SO and SSOP
Reflow soldering Reflow soldering techniques are suitable for all SO and SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300
2003 Sep 12
18
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
2003 Sep 12
19
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
HVQFN20: plastic, heatsink very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm
SOT662-1
2003 Sep 12
20
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
REVISION HISTORY Rev Date _2 20030912
Description Product data (9397 750 12058); ECN 853-2370 30128 dated 18 July 2003. Supersedes data of 2002 September 27 (9397 750 10327). Modifications: * Addition of HVQFN package type. Product data (9397 750 10327); initial version Engineering Change Notice: 853-2370 28875 (2002 Sep 09)
_1
2002 Sep 27
2003 Sep 12
21
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Level
I
Data sheet status[1]
Objective data
Product status[2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 09-03
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 12058
Philips Semiconductors
2003 Sep 12 22

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